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Memory Subsystem Description
The processor board uses industry-standard 60 ns, fast page mode, 72 pin (parity pinout) SIMMs. The
board has 32 SIMM sockets.
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There are four banks in the memory subsystem system, each banks containing eight sockets. Bank
0 is half-populated (four SIMMs) for base memory configurations (128 MB or 256 MB). The first
upgrade must fill the second half of Bank 0, and subsequent upgrades must completely fill each
bank sequentially from Bank 1 to 3. All SIMMs in the memory subsystem must be the same size.
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InterServe 650 and 660 supports three SIMM sizes: 8Mx36 (32 MB), 16Mx36 (64 MB), and
32Mx36 (128 MB). Base systems with 128 MB (four 8Mx36 SIMMs) can be expanded with
8Mx36 SIMMs, for a maximum memory support of 1 GB. Base systems with 256 MB (four
16Mx36 SIMMs) can only be expanded with 16Mx36 SIMMs, for a maximum memory support of
2 GB. Base systems with 512 MB (four 32Mx36 SIMMs) can only be expanded with 32Mx36
SIMMs, for a maximum memory support of 4 GB. Only four SIMMs in Bank 0 are installed for
base memory.
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StudioZ RAX supports two SIMM sizes: 8Mx36 (32 MB), and 16Mx36 (64 MBBase systems
with 256 MB (eight 8Mx36 SIMMs) can be expanded with 8Mx36 SIMMs, for a maximum
memory support of 1 GB. Base systems with 512 MB (eight 16Mx36 SIMMs) can be expanded
with 16Mx36 SIMMs, for a maximum memory support of 2 GB. Eight SIMMs (in Bank 0) are
installed for base memory.
NOTE Systems with BIOS 7640A.ROM support up to 2 GB memory. Systems with BIOS 7640B.ROM or later
support up to 4 GB memory. If your system has version A of the BIOS, you can reprogram the BIOS to
version B. Refer to the
System Setup
for instructions to reprogram the BIOS.
Memory is organized into words, interleaves, and rows.
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Each SIMM generates either the low word (bits 35 to 0) or the high word (bits 71 to 36) of a
72-bit doubleword (8 bits of which are ECC bits) depending on installed location. The low word
and high word sections are split on each side of the board as shown in the following figure. The
high word is called word 1 or W1, and the low word is called word 0 or W0. Due to the design, if
a row in W0 is populated, the same row in W1 (and vice versa) must also be populated for proper
operation. The same memory density SIMM must be used in the row.
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Rows are numbered 0 through 7. Starting at the center of the board and moving out, the first 4
SIMMs on both sides are on row 0 (rows 0 and 1 if the SIMMs are double-sided). The next four
SIMMs are on row 2 (and 3 if double-sided), and so on, through the last (outermost) four SIMMs
on each side of the board, which are on row 6 (and 7 if double-sided).
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Within each row there are four interleaves, designated i0 through i3. Base InterServe
configurations populate i0 and i1 of Row 0/1 for two-way interleave. Base StudioZ RAX
configurations populate i0, i1, i2, and i3 of Row 0/1 for four-way interleave. When upgrades are
installed, all four interleaves of the adjacent rows are populated, yielding four-way interleave for
all installed memory. The correlation between banks and rows is:
Bank 0 Rows 0/1 (i0, i1, i2, i3)
Bank 1 Rows 2/3 (i0, i1, i2, i3)
Bank 2 Rows 4/5 (i0, i1, i2, i3)
Bank 3 Rows 6/7 (i0, i1, i2, i3)
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