ITech IT-M7700 Series - 2.2 Status Register Structure

Status Register
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cleared.
2
3
4
5
6
7
EAV
QUES
MAV
ESB
RQS
OPER
Status Byte Register
Error buffer available.
This bit is set to 1 when any one status of enabled query status register
changes.
Output buffer available.
Bit ESB is set to 1 when the status of an enabled standard event status.
Register changes.
If the status of enabled operation register changes, then this bit is set to1.
2.2 Status Register Structure
The following figure shows the status register structure of the power supply.