372 WM-OM-E Rev I
has a reference "correct" path and will catch differences even if both the reference and the
comparison acquisition are high quality PRML signals. For Channel Emulation with a reference, the
SAM values can be negative, indicating that a different decision was made (less than 0 margin to
the "correct" state). The threshold below which an "error" is flagged is adjustable down to -1, to
permit you to flag places where the DDA’s channel emulation determines a different bit value for the
head signal as compared to the reference head signal. See Channel Emulation With Reference for
a full description of this method.
Channel Emulation without Reference
Channel Emulation without Reference finds a single trace and predicts the bits where the
Sequenced Amplitude Margin (SAM) --- the distance or margin the Viterbi detector has for making a
decision --- is poorest. It uses a full disk drive channel emulation to indicate how the signal ought to
appear when a good reference signal is not available. It measures the SAM of all the samples
(PRML clock locations).
The software emulates a PRML channel and ranks errors by SAM value. A distance or SAM value
of "0" indicates no margin for a decision and the detector’s lack of certainty as to whether the digital
bit should be "1" or "0." The positions of the 100 worst margins are identified and can be displayed
along with the SAM value of each.
Using complete disk drive channel emulation, Channel Emulation without reference predicts where
the head signal quality is the poorest in respect of a PRML channel’s ability to confidently select a
"1" or "0" value.
Channel Emulation without reference starts by finding the beginning of the sector. The algorithm
looks at the head signal beginning at the Read Gate true transition (or analyze region start if Read
Gate is not available) and tries to synchronize to the VCO Synch pattern in order to establish
sampling phase and expected sample levels. To accomplish this, it is required that VCO Synch
Pattern be set correctly, and that the "Bit Cell Time" be approximately correct. The data is then
passed through the emulated channel where it is appropriately sampled. The sampled output
enters the Viterbi detector, which chooses the "sequence" of bits (history) that is the most likely
when the new bit due to this sample is appended. The difference between the mean squared
distance (msd) of the selected sequence and the other possible sequence leading to the selected
state (SAM) is then calculated. For each sample in the Viterbi detector, Channel Emulation without
reference determines a SAM indicating the confidence it has in making a decision between the two
most likely sequences.
If Run Length Limit has a non-zero value, run length limit will also be detected and violations
reported.
If Read Gate is present, it does not necessarily go false immediately after the last byte of valid
information, usually error-correcting code (ECC). The delay is due to the propagation time through
the channel chip and any delays from the controller. Therefore, you can specify the amount of
‘garbage’ data to ignore after the end of the written data and before Read Gate goes false. Errors
detected in this area will be ignored.
When Channel Emulation without reference runs, the ML markers ("+" signs) are automatically
displayed. These show the Maximum Likelihood sample sequence that the channel emulation
chose, based on the signal and the possible sequences. They are drawn at the expected level at
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