Product Principle 4-5
4.2.4 Engine Board
Engine board is equipped with pre-processing of beam data, scanning generator, primary clock on
front-end, ATGC circuit, probe management control, high-voltage switch control, etc. The board is
also considered as the engine of ultrasound service.
Mother
Board
TX_CLK
AFE_CLK
data bus
control bus
JTAG downstream
reset
reset status
rate
presents
manager communication
interrupts
PrbManager_JTAG
various signals
from/to probes. e.g. 4D/TEE
XCVR_REFCLK
PC module
PC Carrier Board
MF FPGA
ATGC Bus
present / UART
power
4D motor signals
temperature /
angle from TEE
ADC SPI
present/ID
config. status
Probe Board
Pen Probe
global reset
PCI-E bus
JTAG downstream
acoustic power IO Board
Psychological
Signal Module
config. status
EC
TR Board
TR FPGA
Engine Board
DAC SPI
4D&TEE
Board
DC-DC Board
scan status
PHV syncPHV Board
DSP
FPGA
Front End Clock Source
IQ DDR
Upload DDR
Clock
Distribution
ATGC
Clock
Control
Data Gathering DDR
BF_CLK
DDR IF
DDR IF
DDR IF
present / ID
Figure 4-5 Schematic diagram of engine board
The functions of engine board:
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