Digital Trunk Clocking
Description
The SL1000/SL1100 CPU has a built-in clock source for all digital trunk units. Digital trunk units are
connected via an internal PLO (Phase Locked Oscillator) to derive Primary Clock from the network in
priority order. If priority is set up incorrectly, or if two primary clocks are coming in, slips may occur
causing improper data synchronization. The Phase Locked Oscillator (PLO) equipped with the
SL1000/SL1100 CPU is the timing source for all digital trunk units in the system. The PLO
synchronizes the system and clocks signals from another office. When the SL1000/SL1100 is a clock
receiver office, the PLO generates the clock signal according to the source clock signals received from
the source office within the network. The source clock signals are extracted from digital trunk units and
are supplied to the PLO.
The PLO synchronization source priorities are as follows:
1. 1PRIU-C1
2. 2BRIDB-C1
3. CPU
Conditions
• If multiple PRIs exist, the system chooses the first one that synchronized with the carrier.
• If there are multiple PRIs and the one being used for the source goes down, the system begins to
count forward in slot numbers looking for the next available PRI.
• If multiple BRIs exist and no 1PRIU-C1 exists, the SL1000/SL1100 CPU chooses the first BRI that
synchronized with the carrier.
• If there is one 1PRIU-C1 and the one being used for the source goes down, the SL1000/SL1100
CPU looks to see if there are any BRIs installed in the system. If there are no BRIs, the SL1000/
SL1100 CPU becomes the new synchronization source. The reason for this is when a 1PRIU-C1 is
installed in the system.
Default Settings
None
System Availability
Terminals
None
Required Component(s)
CPU
2BRIDB-C1 - OR - 1PRIU-C1
ISSUE 2.0
SL1000/SL1100
Features and Specifications Manual 1-193
D
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