2-18 Section 060-INDP-111 System Description
297-6201-502 Standard 01.02 September 2000
PCA Functions
The following subsections describe the PCAs that comprise the BMC.
Central Processor Unit Logic PCA
The CPU PCA is located in slot 1 of the A and B chassis. The CPU, which
has DMA, organizes data flow throughout the BMC. Its operations can be
classified according to the functions of its four major Integrated Circuits
(ICs):
• Z80 IC
• DMA IC
• Counter Timer Circuit (CTC) IC
• Parallel Input/Output (PIO) IC.
The 8-bit microprocessor Z80 IC is responsible for operational, statistical,
and maintenance functions. Some of its activities include communication,
statistics, and log messages. The Z80 microprocessor is driven by the crystal
clock (on the same PCA) through the various program steps.
The DMA IC is a Z80-compatible device, responsible for data transfer to and
from RAM and the TEC/DSI PCAs.
The CTC IC handles interrupts from various devices within the BMC that
request access to the bus for data transfer. The CTC recognizes the priority of
the devices interrupting the normal idle state of the Z80 microprocessor and
directs the Z80 to grant access to the bus according to the importance of the
device making the request.
The PIO Circuit IC is used for all interprocessor communications.
Central processor unit LED display
The CPU PCA contains a seven-segment display LED that provides a visual
display of error control status. Five hardware status lines are decoded to
display CPU fault conditions. The display also contains a decimal point
feature that provides a visual display of the CPU clock. Refer to Table 2-3 for
more information.
Output to the display must occur within 0.5 seconds for the display to remain
valid. This time frame is compatible with the 0.5 second status request time
interval of the Error Control II PCA. The data byte and hardware status lines
are decoded by an EPROM. Output conditions may appear as shown in Table
2-4.
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