NXP Semiconductors MPC5746R - Oscillator and FMPLL

2. Strong pull-down is enabled during power up / phase0 on both pads but after that a weak pull-down is enabled on PORST
and a weak pull-up is enabled on RESET.
10 Oscillator and FMPLL
Two on-chip PLLs, the peripheral clock and reference PLL (PLL0), and the frequency
modulated system PLL (PLL1) generate the system and auxiliary clocks from the
external oscillator.
PLL0
PLL1
RCOSC
XOSC
PLL0_PHI0
PLL0_PHI1
PLL1_PHI0
Figure 8. PLL integration
Table 13. PLL0 electrical characteristics
Symbol Parameter Conditions
Value
Unit
Min Typ Max
f
PLL0IN
PLL0 input clock
1
— 8 — 40 MHz
Δ
PLL0IN
PLL0 input clock duty cycle
1
— 40 — 60 %
f
PLL0VCO
PLL0 VCO frequency — 600 — 1250 MHz
f
PLL0PHI0
PLL0 output clock PHI0 — 4.762 — 400 MHz
t
PLL0LOCK
PLL0 lock time — — — 110 µs
|
Δ
PLL0PHI1SPJ
|
PLL0_PHI1 single period jitter
f
PLL0IN
= 20 MHz (resonator)
f
PLL0PHI1
= 40 MHz, 6-
sigma
— — 300
2
ps
Δ
PLL0LTJ
PLL0 output long term jitter
2
f
PLL0IN
= 20 MHz (resonator), VCO
frequency = 800 MHz
10 periods accumulated
jitter (80 MHz frequency),
6-sigma pk-pk
–250 — 250 ps
16 periods accumulated
jitter (50 MHz frequency),
6-sigma pk-pk
–300 — 300 ps
long term jitter
(< 1MHz frequency), 6-
sigma pk-pk
–650 — 650 ps
I
PLL0
PLL0 consumption FINE LOCK state — — 5 mA
1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted
when using internal RCOSC or external oscillator is used in functional mode.
Oscillator and FMPLL
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
22 NXP Semiconductors