NXP Semiconductors MPC5746R - DSPI Timing with CMOS and LVDS

Tx Data [m]
Zero Crossover
CLOCK
REF
CLOCK
REF
1a
1
2
8
9
9
8 8
2
1a
1a
1a
Zero Crossover
Tx Data
Tx Data
Tx Data [n]
Ideal Zero Crossover
Zero Crossover
Tx Data [n+1]
Zero Crossover
Figure 29. Aurora timings
18.2
DSPI timing with CMOS and LVDS
DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel
bus protocol.
DSPI channel frequency support is shown in Table 39. Timing specifications are shown
in Table 40, Table 41, Table 42, Table 43, Table 44.
Table 39. DSPI channel frequency support
DSPI use mode
Max usable frequency
(MHz)
1
,
2
CMOS (Master mode) Full duplex – Classic timing (Table 40) 17
Full duplex – Modified timing (Table 41) 30
Output only mode (SCK/SOUT/PCS) (Table 40 and Table 41) 30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 44) 30
LVDS (Master mode) Full duplex – Modified timing (Table 42) 40
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 65