17.6 Flash read wait state and address pipeline control settings
Table 34 describes the recommended RWSC and APC settings at various operating
frequencies based on specified intrinsic flash access times of the C55FMC array at 150
°C.
Table 34. Flash Read Wait State and Address Pipeline Control Guidelines
Operating Frequency
f
SYS
RWSC APC
Flash read latency on mini-
cache miss (# of f
SYS
clock
periods)
Flash read latency on mini-
cache hit (# of f
SYS
clock
periods)
30 MHz 0 0 3 1
100 MHz 2 1 5 1
133 MHz 3 1 6 1
167 MHz 4 1 7 1
200 MHz 5 2 8 1
18 AC specifications
18.1 Debug and calibration interface timing
18.1.1 JTAG interface timing
These specifications apply to JTAG boundary scan only. See Table 36 for functional
specifications.
Table 35. JTAG pin AC electrical characteristics
# Symbol Characteristic
Value
Unit
Min Max
1 t
JCYC
TCK cycle time 100 — ns
2 t
JDC
TCK clock pulse width 40 60 ns
3 t
TCKRISE
TCK rise and fall times — 3 ns
4 t
TMSS
, t
TDIS
TMS, TDI data setup time 5 — ns
5 t
TMSH
, t
TDIH
TMS, TDI data hold time 5 — ns
6 t
TDOV
TCK low to TDO data valid — 16
1
ns
Table continues on the next page...
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
58 NXP Semiconductors
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