4. t
SDC
is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
5. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
PCSx
SCK Output
(CPOL = 0)
SOUT
First Data
Last Data
Data
t
SUO t
HO
t
CSV
t
SDC
t
SCK
t
CSH
Figure 38. DSPI LVDS and CMOS master timing – output only – modified transfer format
MTFE = 1, CHPA = 1
18.2.2 DSPI CMOS slave mode
NOTE
DSPI slave operation is only supported for a single master and
single slave on the device. Timing is valid for that case only.
Table 45. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1)
# Symbol Characteristic
1
Condition Value Unit
Pad drive Load Min Max
1 t
SCK
SCK Cycle Time — — 62 — ns
2 t
CSC
SS to SCK Delay — — 16 — ns
3 t
ASC
SCK to SS Delay — — 16 — ns
4 t
SDC
SCK Duty Cycle — — 30 — ns
5 t
A
Slave Access Time
2
(SS active to SOUT
driven)
Very strong 25 pF — 50 ns
Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
6 t
DIS
Slave SOUT Disable
Time
2
(SS inactive to SOUT
High-Z or invalid)
Very strong 25 pF — 5 ns
Strong 50 pF — 5 ns
Medium 50 pF — 10 ns
9 t
SUI
Data Setup Time for
Inputs
— — 10 — ns
Table continues on the next page...
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
78 NXP Semiconductors
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