Table 44. DSPI CMOS master timing - output only - timed serial bus mode TSB = 1 or ITSB =
1, CPOL = 0 or 1, continuous SCK clock
# Symbol Characteristic Condition Value
1
Unit
Pad drive
2
Load (C
L
) Min Max
1 t
SCK
SCK cycle time SCK drive strength
Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 — ns
Medium 50 pF 200.0 — ns
2 t
CSV
PCS valid after SCK
3
SCK and PCS drive strength
Very strong 25 pF 7 — ns
Strong 50 pF 8 — ns
Medium 50 pF 16 — ns
PCS medium and
SCK strong
PCS = 50 pF
SCK = 50 pF
29 — ns
3 t
CSH
PCS hold after SCK
3
SCK and PCS drive strength
Very strong PCS = 0 pF
SCK = 50 pF
-14 — ns
Strong PCS = 0 pF
SCK = 50 pF
-14 — ns
Medium PCS = 0 pF
SCK = 50 pF
-33 — ns
PCS medium and
SCK strong
PCS = 0 pF
SCK = 50 pF
-35 — ns
4 t
SDC
SCK duty cycle
4
SCK drive strength
Very strong 0 to 50 pF
1
/
2
t
SCK
- 2
1
/
2
t
SCK
+ 2 ns
Strong 0 to 50 pF
1
/
2
t
SCK
- 2
1
/
2
t
SCK
+ 2 ns
Medium 0 to 50 pF
1
/
2
t
SCK
- 5
1
/
2
t
SCK
+ 5 ns
SOUT data valid time (after SCK edge)
9 t
SUO
SOUT data valid time
from SCK
CPHA = 1
, 5
SOUT and SCK drive strength
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0 ns
Medium 50 pF — 16.0 ns
SOUT data hold time (after SCK edge)
10 t
HO
SOUT data hold time
after SCK CPHA = 1
5
SOUT and SCK drive strength
Very strong 25 pF -7.7 — ns
Strong 50 pF -11.0 — ns
Medium 50 pF -15.0 — ns
1. All timing values for output signals in this table are measured to 50% of the output voltage.
2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 77
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