NXP Semiconductors MPC5746R - Page 76

• All DSPI timing specifications apply to pins when using LVDS pads for SCK and
SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may
degrade for weaker output drivers.
• TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
Table 43. DSPI LVDS master timing - output only - timed serial bus mode TSB = 1 or ITSB =
1, CPOL = 0 or 1, continuous SCK clock
# Symbol Characteristic Condition Value Unit
Pad drive Load Min Max
1 t
SCK
SCK cycle time LVDS 15 pF
to 50 pF
differential
25.0 — ns
2 t
CSV
PCS valid after SCK
1
(SCK with 50 pF
differential load cap.)
Very strong 25 pF — 6.0 ns
Strong 50 pF — 6.0 ns
3 t
CSH
PCS hold after SCK
1
(SCK with 50 pF
differential load cap.)
Very strong 0 pF -4.0 — ns
Strong 0 pF -4.0 — ns
4 t
SDC
SCK duty cycle
(SCK with 50 pF
differential load cap.)
LVDS 15 pF
to 50 pF
differential
1
/
2
t
SCK
- 2
1
/
2
t
SCK
+ 2 ns
SOUT data valid time (after SCK edge)
5 t
SUO
SOUT data valid time
from SCK
2
SOUT and SCK drive strength
LVDS 15 pF
to 50 pF
differential
— 3.5 ns
SOUT data hold time (after SCK edge)
6 t
HO
SOUT data hold time
after SCK
2
SOUT and SCK drive strength
LVDS 15 pF
to 50 pF
differential
-3.5 — ns
1. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
2. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
For Table 44 :
• TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
• All output timing is worst case and includes the mismatching of rise and fall times of
the output pads.
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
76 NXP Semiconductors