R6
REF_CLK (input)
TXD[1:0] (outputs)
TX_EN
R7
R5
R8
Figure 47. RMII transmit signal timing diagram
18.4
UART timings
UART channel frequency support is shown in the following table.
Table 53. UART frequency support
LINFlexD clock frequency
LIN_CLK (MHz)
Oversampling rate Voting scheme Max usable frequency
(Mbaud)
80 16 3:1 majority voting 5
8 10
6 Limited voting on one sample
with configurable sampling
point
13.33
5 16
4 20
18.5 eMIOS timing
Table 54. eMIOS timing
Symbol Characteristic Condition Min.
Value
Max.
Value
Unit
t
MIPW
eMIOS Input Pulse Width eMIOS_CLK = 100 MHz 2 — cycles
19 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing's document number.
Obtaining package dimensions
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
86 NXP Semiconductors
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