NXP Semiconductors MPC5746R - RMII Receive Signal Timing (RXD[1:0], CRS_DV)84

Table 50. RMII serial management channel timing (continued)
Spec Characteristic
Value Unit
Min Max
M11 MDC falling edge to
MDIO output valid (max
prop delay)
— 25 ns
M12 MDIO (input) to MDC
rising edge setup
10 — ns
M13 MDIO (input) to MDC
rising edge hold
0 — ns
M14 MDC pulse width high 40% 60% MDC period
M15 MDC pulse width low 40% 60% MDC period
MDC (output)
MDIO (output)
MDIO (input)
M12
M13
M10
M15
M14
M11
Figure 45. RMII-lite serial management channel timing diagram
18.3.6
RMII receive signal timing (RXD[1:0], CRS_DV)
The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at
least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK
frequency.
All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels.
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
84 NXP Semiconductors