NXP Semiconductors MPC5746R - MII-Lite Transmit Signal Timing; Tx_En, Tx_Er, Tx_Clk)

M3
M4
M1
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
RX_ER
M2
Figure 41. MII-lite receive signal timing diagram
18.3.2 MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER,
TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz
+1%. There is no minimum frequency requirement. The system clock frequency must be
at least equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case.
This options allows the use of non-compliant MII PHYs.
All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels.
Table 47. MII-lite transmit signal timing
Spec Characteristic
Value
1
Unit
Min Max
M5 TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 — ns
M6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid — 25 ns
M7 TX_CLK pulse width high 35% 65% TX_CLK period
M8 TX_CLK pulse width low 35% 65% TX_CLK period
1. Output parameters are valid for C
L
= 25 p
F
, where CL is the external load to the device. The internal package capacitance
is accounted for, and does not need to be subtracted from the 25 p
F
value.
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 81