NXP Semiconductors MPC5746R - Page 75

Data
Data
Last Data
First Data
First Data
Last Data
SIN
SOUT
SCK Output
SCK OutputSCK Output
(CPOL = 0)
PCSx
(CPOL = 1)
t
SCK
t
SDC
t
SDC
CSC
t
t
ASC
t
t
SUI
HI
t
SUO
t
HO
Figure 36. DSPI LVDS master mode – modified timing, CPHA = 0
Data
First Data
First Data
Last Data
Data
Last Data
SIN
PCSx
SCK Output
SCK Output
(CPOL = 0)
(CPOL = 1)
SOUT
t
SUI
t
t
HI
HI
t
SUO
t
HO
Figure 37. DSPI LVDS master mode – modified timing, CPHA = 1
18.2.1.4
DSPI master mode – output only
For Table 43 :
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 75