NXP Semiconductors MPC5746R - Page 69

SCK Output
SIN
SOUT
Fist Data
Fist Data
Last Data
Last Data
Data
Data
SCK Output
(CPOL = 0)
PCSx
(CPOL = 1)
t
t
t
t
SUI
HI
SUO
HO
Figure 31. DSPI CMOS master mode – classic timing, CPHA = 1
PCSx
PCSS
t
PCSC
t
PASC
Figure 32. DSPI PCS strobe (PCSS) timing (master mode)
18.2.1.2
DSPI CMOS master mode – modified timing
All output timing is worst case and includes the mismatching of rise and fall times of the
output pads.
NOTE
In Table 41, all output timing is worst case and includes the
mismatching of rise and fall times of the output pads.
Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1,
CPHA = 0 or 1
# Symbol Characteristic Condition Value
1
Unit
Pad drive
2
Load (C
L
) Min Max
1 t
SCK
SCK cycle time SCK drive strength
Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Table continues on the next page...
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 69