NXP Semiconductors MPC5746R - Page 73

PCSx
PCSS
t
PCSC
t
PASC
Figure 35. DSPI PCS strobe (PCSS) timing (master mode)1
18.2.1.3 DSPI LVDS master mode – modified timing
Table 42. DSPI LVDS master timing - full duplex - modified transfer format (MTFE = 1),
CPHA = 0 or 1
# Symbol Characteristic Condition Value
1
Unit
Pad drive Load Min Max
1 t
SCK
SCK cycle time LVDS 15 pF
to 25 pF
differential
30.0 — ns
2 t
CSC
PCS to SCK delay
(LVDS SCK)
PCS drive strength
Very strong 25 pF (N
2
x t
SYS
, 3
) - 10 — ns
Strong 50 pF (N
2
x t
SYS
, 3
) - 10 — ns
Medium 50 pF (N
2
x t
SYS
, 3
) - 32 — ns
3 t
ASC
After SCK delay
(LVDS SCK)
Very strong PCS = 0 pF
SCK = 25 pF
(M
4
x t
SYS
3
) - 8 — ns
Strong PCS = 0 pF
SCK = 25 pF
(M
4
x t
SYS
, 3
) - 8 — ns
Medium PCS = 0 pF
SCK = 25 pF
(M
4
x t
SYS
, 3
) - 8 — ns
4 t
SDC
SCK duty cycle
5
LVDS 15 pF
to 25 pF
differential
1
/
2
t
SCK
- 2
1
/
2
t
SCK
+ 2 ns
7 t
SUI
SIN setup time
SIN setup time to
SCK
CPHA = 0
6
SCK drive strength
LVDS 15 pF
to 25 pF
differential
23 - (P
7
x t
SYS
3
) — ns
SIN setup time to
SCK
CPHA = 1
6
SCK drive strength
LVDS 15 pF
to 25 pF
differential
23 — ns
8 t
HI
SIN Hold Time
Table continues on the next page...
AC specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 73