NXP Semiconductors MPC5746R - SDn ADC Electrical Specification

Functional operating conditions are given in the DC electrical specifications. Absolute
maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the listed maxima may affect device reliability or cause
permanent damage to the device.
Table 20. SDn ADC electrical specification
Symbol Parameter Conditions
Value
Unit
Min Typ Max
V
IN
ADC input signal — 0 — V
DD_HV_
ADV_SD
V
V
IN_PK2PK
1
Input range peak to
peak
V
IN_PK2PK
= V
INP
2
–
V
INM
, 3
Single ended.
V
INM
= V
SS_HV_ADR_SD
V
DD_HV_ADR_SD
/GAIN
V
Single ended.
V
INM
= 0.5*V
DD_HV_ADR_SD
GAIN = 1
±0.5*V
DD_HV_ADR_SD
Single ended.
V
INM
= 0.5*V
DD_HV_ADR_SD
GAIN = 2,4,8,16
±V
DD_HV_ADR_SD
/GAIN
Differential
0 < V
IN
< V
DD_HV_IO_MAIN
±V
DD_HV_ADR_SD
/GAIN
f
ADCD_M
S/D clock frequency T
J
< 150 °C 4 14.4 16 MHz
f
ADCD_S
Conversion rate T
J
< 150 °C — — 333 ksps
— Oversampling ratio Internal modulator 24 — 256 —
RESOLUTION S/D register resolution 2's complement notation 16
4
bit
GAIN ADC gain Defined through ADC_SD[PGA] register.
Only integer power of 2 are valid gain.
1 — 16 —
|δ
GAIN
| Absolute value of the
ADC gain error
5
Before calibration (applies to gain
settings =1)
— — 1 %
After calibration
6
Δ V
DD_HV_ADR_SD
< 5%
Δ V
DD_HV_ADV_SD
< 10%
T
J
< 50 °C
— — 0.1 %
After calibration
6
Δ V
DD_HV_ADR_SD
< 5%
Δ V
DD_HV_ADV_SD
< 10%
T
J
< 150 °C
— — 0.2 %
V
OFFSET
Conversion offset Before calibration
(applies to all gain settings – 1, 2, 4, 8,
16)
— 10*
(1+1/
gain)
20 mV
After calibration
6
— — 5 mV
SNR
DIFF150
, 7
Signal to noise ratio in
differential mode 150
ksps output rate
4.5 < V
DD_HV_ADV_SD
< 5.5
7
V
DD_HV_ADR_D
= V
DD_HV_ADV_D
78 — — dB
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ADC modules
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
30 NXP Semiconductors