NXP Semiconductors MPC5777M - Page 107

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 107
Figure 37. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1, CHPA = 1
3.16.2.2 Slave Mode timing
6
t
SDC
is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Table 57. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)
1
# Symbol Characteristic
Condition
Min Max Unit
Pad Drive Load
1t
SCK
CC SCK Cycle Time
2
- - 62 —ns
2t
CSC
SR SS to SCK Delay
2
- - 16 —ns
3t
ASC
SR SCK to SS Delay
2
- - 16 —ns
4t
SDC
CC SCK Duty Cycle
2
- -30 —ns
5t
A
CC Slave Access Time
2,3,4
(SS active to SOUT driven)
Very
Strong
25 pF — 50 ns
Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
6t
DIS
CC Slave SOUT Disable
Time
2,3,4
(SS inactive to SOUT High-Z
or invalid)
Very
Strong
25 pF — 5ns
Strong 50 pF — 5ns
Medium 50 pF — 10 ns
9t
SUI
CC Data Setup Time for Inputs
2
— — 10 — ns
10 t
HI
CC Data Hold Time for Inputs
2
— — 10 — ns
PCSx
SCK Output
SOUT
First Data
Data
Last Data
(CPOL = 0)
t
SUO t
HO
t
CSV
t
SDC
t
SCK
t
CSH