NXP Semiconductors QorIQ LS1043ARDB - Page 4

Section number Title Page
3.2.2 Power sequencing................................................................................................................................................ 34
3.3 CPLD controller................................................................................................................................................................35
3.3.1 CPLD features......................................................................................................................................................35
3.3.2 CPLD block diagram........................................................................................................................................... 36
3.3.3 CPLD registers.....................................................................................................................................................37
3.4 Power-on reset.................................................................................................................................................................. 38
3.4.1 Reset configuration signals.................................................................................................................................. 39
3.4.2 Reset architecture.................................................................................................................................................40
3.5 DDR supply...................................................................................................................................................................... 41
3.6 POVDD supply.................................................................................................................................................................42
Chapter 4
Clocks, Interrupts, and Temperature Monitoring
4.1 Clocking scheme...............................................................................................................................................................43
4.2 Clock frequency selection.................................................................................................................................................44
4.3 MPIC controller................................................................................................................................................................ 45
4.4 Temperature anode and cathode....................................................................................................................................... 45
Chapter 5
Debug and Input/Output
5.1 ARM/JTAG architecture...................................................................................................................................................47
5.2 CMSIS-DAP..................................................................................................................................................................... 48
5.3 GPIOs................................................................................................................................................................................49
Chapter 6
CPLD Programming
6.1 CPLD memory map / register definitions.........................................................................................................................51
6.1.1 CPLD major version register (CPLD_VER)....................................................................................................... 52
6.1.2 CPLD minor version register (CPLD_VER_SUB)............................................................................................. 52
6.1.3 PCBA version register (CPLD_PCBA_VER)..................................................................................................... 53
6.1.4 System reset register (CPLD_SYSTEM_RST)................................................................................................... 53
6.1.5 CPLD override physical switches enable register (CPLD_SOFT_MUX_ON)...................................................54
6.1.6 POR RCW source location register 1 (CPLD_REG_RCW_SRC1)....................................................................55
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
4 NXP Semiconductors