NXP Semiconductors QorIQ LS1043ARDB - Page 5

Section number Title Page
6.1.7 POR RCW source location register 2 (CPLD_REG_RCW_SRC2)....................................................................56
6.1.8 Flash bank selection register (CPLD_REG_BANK)...........................................................................................56
6.1.9 System clock single-ended or differential input selection register (CPLD_SYSCLK_SEL)..............................57
6.1.10 UART1 output selection register (CPLD_UART_SEL)..................................................................................... 58
6.1.11 SerDes PLL1 reference clock input selection register (CPLD_SD1REFCLK_SEL)..........................................58
6.1.12 TDM clock or SDHC/USB selection register (CPLD_TDMCLK_MUX_SEL).................................................59
6.1.13 Status LED control register (CPLD_STATUS_LED).........................................................................................60
6.1.14 Global reset register (CPLD_GLOBAL_RST)....................................................................................................60
6.1.15 TDM riser card presence detection register (CPLD_TDMR_PRS_N)................................................................61
6.1.16 RTC clock assignment register (CPLD_REG_RTC)...........................................................................................61
6.1.17 EVDD control register (CPLD_EVDD_SEL)..................................................................................................... 62
6.1.18 CPLD register override physical switch SDHC_VS/SPI_CS0 enable register (CPLD_SOFT_VS_SPICS0)....62
6.1.19 SDHC_VS or SPI_CS0 selection register (CPLD_VS_SPICS0_SEL)...............................................................63
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 5