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Omron CP1H CPU User Manual

Omron CP1H CPU
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143
Overview of I/O Memory Area Section 4-1
Note 1. H512 to H1535 are used as a Function Block Holding Area. These words
can be used only for function block instances (internally allocated variable
area).
2. Bits can be manipulated using TST(350), TSTN(351), SET, SETB(532),
RSTB(533), and OUTB(534).
3. Index registers and data registers can be used either individually by task
or they can be shared by all the tasks (the default is individual use by task).
4. Timer PVs can be refreshed indirectly by force-setting/resetting the Timer
Completion Flags.
5. Counter PVs can be refreshed indirectly by force-setting/resetting the
Counter Completion Flags.
TR Area 16 bits TR0 to
TR15
Shared by
all tasks
--- OK OK OK OK No No
Data Memory Area 32,768
words
D00000
to
D32767
--- No
(Note
2)
OK OK OK OK No
Timer Completion Flags 4,096 bits T0000 to
T4095
--- OK --- OK OK OK OK
Counter Completion Flags 4,096 bits C0000 to
C4095
--- OK --- OK OK OK OK
Timer PVs 4,096
words
T0000 to
T4095
--- --- OK OK OK OK No
(Note 4)
Counter PVs 4,096
words
C0000 to
C4095
--- --- OK OK OK OK No
(Note 5)
Task Flag Area 32 bits TK0 to
TK31
--- OK --- OK No No No
Index Registers 16 regis-
ters
IR0 to
IR15
Function
separately in
each task
(Note 3)
--- OK OK Indirect
address-
ing only
Specific
instruc-
tions only
No No
Data Registers 16 regis-
ters
DR0 to
DR15
--- No OK OK OK No No
Area Size Range Task usage Allocation Bit
access
Word
access
Access Change
from CX-
Programmer
Forcing
bit
status
Read Write

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Omron CP1H CPU Specifications

General IconGeneral
BrandOmron
ModelCP1H CPU
CategoryComputer Hardware
LanguageEnglish

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