Omron CP1H CPU User Manual

165
Timers and Counters Section 4-13
Examples In this example, a TR bit is used when two outputs have been directly con-
nected to a branch point.
In this example, a TR bit is used when an output is connected to a branch
point without a separate execution condition.
Note A TR bit is not required when there are no execution conditions after the
branch point or there is an execution condition only in the last line of the
instruction block.
4-13 Timers and Counters
4-13-1 Timer Area (T)
The 4,096 timer numbers (T0000 to T4095) are shared by the TIM,
TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TIMHHX(552), TTIM(087),
TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TIMHWX(817)
instructions. Timer Completion Flags and present values (PVs) for these
instructions are accessed with the timer numbers.
The TIML(542), TIMLX(553), MTIM(543), and MTIMX(554) instructions do not
use timer numbers.
When a timer number is used in an operand that requires bit data, the timer
number accesses the Completion Flag of the timer. When a timer number is
used in an operand that requires word data, the timer number accesses the
PV of the timer. Timer Completion Flags can be used as often as necessary
as normally open and normally closed conditions and the values of timer PVs
can be read as normal word data.
LD
OR
OUT
AND
OUT
LD
AND
OUT
0.00
0.01
TR 0
0.02
0.03
TR 0
0.04
0.05
Instruction
Operand
TR0
0.00
0.05
0.01
0.02
0.04
0.03
LD
OUT
AND
OUT
LD
OUT
0.00
TR 0
0.01
0.02
TR 0
0.03
Instruction
Operand
TR0 0.00
0.01 0.02
0.03
LD
0.00
OUT
0.01
AND
OUT
0.02
0.03
LD
0.00
OUT
OUT
0.01
0.02
Instruction Operand
Instruction Operand
0.00
0.01
0.02
0.00
0.01
0.03
0.02

Omron CP1H CPU Specifications

General

Brand	Omron
Model	CP1H CPU
Category	Computer Hardware
Language	English