Omron CP1H CPU

644
Auxiliary Area Allocations by Address Appendix D
A264
and
A265
All Present Cycle
Time
These words contain the present
cycle time in 8-digit hexadecimal with
the leftmost 4 digits in A265 and the
rightmost 4 digits in A264.
0 to
FFFFFFFF:
0 to
429,496,729.
5 ms
--- --- --- ---
A270
to
A271
All High-speed
Counter 0 PV
Contains the PV of high-speed
counter 0. A271 contains the left-
most 4 digits and A270 contains the
rightmost 4 digits.
The PV is cleared when operation
starts.
--- --- Cleared Refreshed
each cycle
during
oversee
process.
Refreshed
when
PRV(881)
instruction
is exe-
cuted.
---
A272
to
A273
All High-speed
Counter 1 PV
Contains the PV of high-speed
counter 1. A273 contains the left-
most 4 digits and A272 contains the
rightmost 4 digits.
The PV is cleared when operation
starts.
--- --- Cleared Refreshed
each cycle
during
oversee
process.
Refreshed
when
PRV(881)
instruction
is exe-
cuted.
---
A274 A274.00 High-speed
Counter 0
Range 1 Com-
parison Condi-
tion Met Flag
These flags indicate whether the PV
is within the specified ranges when
high-speed counter 0 is being oper-
ated in range-comparison mode.
Cleared at beginning of operation.
Cleared when range comparison
table is registered.
OFF: PV not in range
ON: PV in range
--- --- Cleared Refreshed
each cycle
during
oversee
process.
Refreshed
when
PRV(881)
instruction
is exe-
cuted.
---
A274.01 High-speed
Counter 0
Range 2 Com-
parison Condi-
tion Met Flag
A274.02 High-speed
Counter 0
Range 3 Com-
parison Condi-
tion Met Flag
A274.03 High-speed
Counter 0
Range 4 Com-
parison Condi-
tion Met Flag
A274.04 High-speed
Counter 0
Range 5 Com-
parison Condi-
tion Met Flag
A274.05 High-speed
Counter 0
Range 6 Com-
parison Condi-
tion Met Flag
A274.06 High-speed
Counter 0
Range 7 Com-
parison Condi-
tion Met Flag
A274.07 High-speed
Counter 0
Range 8 Com-
parison Condi-
tion Met Flag
Address Name Function Settings Status
after
mode
change
Status
at star-
tup
Write
timing
Related
flags, set-
tings
Words Bits