6-13
High-speed counter/pulse output control flag area of FPΣ
• The area DT90052 for writing channels
and control codes is allocated as shown in
the left figure.
• Control codes written with an F0 (MV)
instruction are stored by channel in
special data registers DT90190 to
DT90193.
Note) In the reset input setting, the reset
input (X2 or X5) allocated in the high-speed
counter setting of the system registers are
defined to “enable/disable”.
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