Siemens Argus 7SR21 - Figure 3.1.3-1 Logic Diagram: Time Delayed Overcurrent Element

7SR210 & 7SR220 Description of Operation
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1
1
General Pickup
51-n
If directional elements are not present this block is
omitted and all 'Lx Dir En' signals are set TRUE.
51-n Setting
51-n Charact
51-n Time Mult
51-n Delay (DTL)
51-n Reset
c
Forward
Reverse
51-n Dir Control
Non-Dir
1
&
&
1
&
&
1
&
&
51-n Follower DTL
L1 Dir En
L2 Dir En
L3 Dir En
L1 Dir En
L2 Dir En
L3 Dir En
IL1 Fwd
IL1 Rev
IL2 Fwd
IL2 Rev
IL3 Fwd
IL3 Rev
&
&
&
1
1
1
Non Dir
51-n VTS Action
Off
Inhibit
60VTS
&
51-n Min. Operate Time
&
IL1
IL2
IL3
50/51
Measurement
&
See Voltage Controlled
Overcurrent (51V)
L1 81HBL2
51c
51-n Inrush
Action
Off
Inhibit
&
L3
L2
L1
L2 81HBL2
L3 81HBL2
&
&
&
&
&
c
Pickup
trip
c
Pickup
trip
c
Pickup
trip
Inhibit 51-n
51-n Element
Enabled
Disabled
&
79 P/F Inst Trips
= 51-n
79 P/F Prot’n Trip n
= Delayed
AUTORECLOSE
NB: For a comprehensive
list of input & output signals
see Data Comms Definitions
Inhibit 51-n
51-n
General Pickup
Figure 3.1.3-1 Logic Diagram: Time Delayed Overcurrent Element