HAP-S1
87
Pin No. Pin Name I/O Description
C9 RTC_XTALO O Real time clock output terminal (32.768 kHz)
C10 GND24 - Ground terminal
C11 POR_B I Reset signal input from reset signal generator and system controller “L”: reset
C12 BOOT_MODE0 I Boot mode setting terminal Fixed at “L”
C13 SD3_DAT5 - Not used
C14 SATA_REXT - Terminal for the impedance calibration
C15 NANDF_CLE O Update signal output to the system controller “H”: update
C16 NANDF_CS1 O Reset signal output terminal Not used
C17 NANDF_D1 I/O Two-way data bus terminal Not used
C18 NANDF_D7 - Not used
C19 SD4_DAT5 I/O Two-way data bus with the fl ash memory
C20 SD1_DAT1 I/O Two-way data bus terminal Not used
C21 SD2_CLK - Not used
C22 RGMII_TD0 O RGMII transmit data output to the ethernet transceiver
C23 RGMII_TX_CTL O RGMII transmit data enable signal output to the ethernet transceiver
C24 RGMII_RD0 I RGMII receive data input from the ethernet transceiver
C25 EIM_D16 - Not used
D1 CSI_D1M - Not used
D2 CSI_D1P - Not used
D3 GND27 - Ground terminal
D4 CSI_REXT - Not used
D5 CLK2_P - Not used
D6 GND28 - Ground terminal
D7 CLK1_P O Clock signal (positive) output to the FPGA
D8 GND29 - Ground terminal
D9 RTC_XTALI I Real time clock input terminal (32.768 kHz)
D10 USB_H1_VBUS I Power supply of the USB interface for the WLAN/BT COMBO card
D11 PMIC_ON_REQ O Not used
D12 ONOFF - Not used
D13 SD3_DAT4 - Not used
D14 SD3_CLK - Not used
D15 SD3_RST - Not used
D16 NANDF_CS3 - Not used
D17 NANDF_D3 - Not used
D18, D19
SD4_DAT0,
SD4_DAT7
I/O Two-way data bus with the fl ash memory
D20 SD1_CLK O Clock signal output terminal Not used
D21 RGMII_TXC O RGMII transmit clock signal output to the ethernet transceiver
D22 RGMII_RX_CTL I RGMII receive data valid signal input from the ethernet transceiver
D23 RGMII_RD3 I RGMII receive data input from the ethernet transceiver
D24 EIM_D18 - Not used
D25 EIM_D23 I Status signal input from the FPGA
E1 CSI_D2M - Not used
E2 CSI_D2P - Not used
E3 CSI_D0P - Not used
E4 CSI_D0M - Not used
E5 to E7 GND30 to GND32 - Ground terminal
E8 NVCC_PLL_OUT - Power supply terminal for the PLL output Not used
E9 USB_OTG_VBUS I Power supply of the USB interface for the USB connector
E10 USB_H1_DP I/O Two-way USB data (positive) with the WLAN/BT COMBO card
E11 TAMPER I Mode setting terminal Fixed at “H”
E12 TEST_MODE I Mode setting terminal Not used
E13 SD3_DAT6 - Not used
E14 SD3_DAT0 - Not used
E15 NANDF_WP_B O LED drive signal output terminal “H”: LED on
E16 SD4_CLK O Clock signal output to the fl ash memory
E17 NANDF_D6 - Not used
E18 SD4_DAT4 I/O Two-way data bus with the fl ash memory
E19 SD1_DAT2 I/O Two-way data bus terminal Not used
E20 SD2_DAT1 - Not used