Reset and clock control (RCC)
ï‚· The PLL can not be disabled if it is used as system clock
source
ï‚· The PLL is disabled by hardware when entering STOP and
STANDBY modes.
18.2.6.11 RCC_PREDIV1Config
void RCC_PREDIV1Config ( uint32_t RCC_PREDIV1_Div)
Configures the PREDIV1 division factor.
ï‚· RCC_PREDIV1_Div : specifies the PREDIV1 clock division
factor. This parameter can be RCC_PREDIV1_Divx where
x:[1,16]
ï‚· This function must be used only when the PLL is disabled.
18.2.6.12 RCC_ClockSecuritySystemCmd
void RCC_ClockSecuritySystemCmd ( FunctionalState
NewState)
Enables or disables the Clock Security System.
ï‚· NewState : new state of the Clock Security System. This
parameter can be: ENABLE or DISABLE.
ï‚· If a failure is detected on the HSE oscillator clock, this
oscillator is automatically disabled and an interrupt is
generated to inform the software about the failure (Clock
Security System Interrupt, CSSI), allowing the MCU to
perform rescue operations. The CSSI is linked to the Cortex-
M4 NMI (Non-Maskable Interrupt) exception vector.
18.2.6.13 RCC_MCOConfig