ST STM32F31xx - Page 320

Reset and clock control (RCC)
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Notes
 After enabling the LSI, the application software should wait on
LSIRDY flag to be set indicating that LSI clock is stable and
can be used to clock the IWDG and/or the RTC.
 LSI can not be disabled if the IWDG is running.
 When the LSI is stopped, LSIRDY flag goes low after 6 LSI
oscillator clock cycles.
18.2.6.9 RCC_PLLConfig
Function Name
void RCC_PLLConfig ( uint32_t RCC_PLLSource, uint32_t
RCC_PLLMul)
Function Description
Configures the PLL clock source and multiplication factor.
Parameters
 RCC_PLLSource : specifies the PLL entry clock source.
This parameter can be one of the following values:
 RCC_PLLSource_HSI_Div2 : HSI oscillator clock
divided by 2 selected as PLL clock entry
 RCC_PLLSource_PREDIV1 : PREDIV1 clock selected
as PLL clock source
 RCC_PLLMul : specifies the PLL multiplication factor, which
drive the PLLVCO clock This parameter can be
RCC_PLLMul_x where x:[2,16]
Return values
 None.
Notes
 This function must be used only when the PLL is disabled.
 The minimum input clock frequency for PLL is 2 MHz (when
using HSE as PLL source).
18.2.6.10 RCC_PLLCmd
Function Name
void RCC_PLLCmd ( FunctionalState NewState)
Function Description
Enables or disables the PLL.
Parameters
 NewState : new state of the PLL. This parameter can be:
ENABLE or DISABLE.
Return values
 None.
Notes
 After enabling the PLL, the application software should wait
on PLLRDY flag to be set indicating that PLL clock is stable
and can be used as system clock source.