ST STM32F31xx

Reset and clock control (RCC)
UM1581
324/584
DocID023800 Rev 1
details refer to section above "CPU, AHB and APB busses
clocks configuration functions").
18.2.7.4 RCC_PCLK1Config
Function Name
void RCC_PCLK1Config ( uint32_t RCC_HCLK)
Function Description
Configures the Low Speed APB clock (PCLK1).
Parameters
 RCC_HCLK : defines the APB1 clock divider. This clock is
derived from the AHB clock (HCLK). This parameter can be
one of the following values:
 RCC_HCLK_Div1 : APB1 clock = HCLK
 RCC_HCLK_Div2 : APB1 clock = HCLK/2
 RCC_HCLK_Div4 : APB1 clock = HCLK/4
 RCC_HCLK_Div8 : APB1 clock = HCLK/8
 RCC_HCLK_Div16 : APB1 clock = HCLK/16
Return values
 None.
Notes
 None.
18.2.7.5 RCC_PCLK2Config
Function Name
void RCC_PCLK2Config ( uint32_t RCC_HCLK)
Function Description
Configures the High Speed APB clock (PCLK2).
Parameters
 RCC_HCLK : defines the APB2 clock divider. This clock is
derived from the AHB clock (HCLK). This parameter can be
one of the following values:
 RCC_HCLK_Div1 : APB2 clock = HCLK
 RCC_HCLK_Div2 : APB2 clock = HCLK/2
 RCC_HCLK_Div4 : APB2 clock = HCLK/4
 RCC_HCLK_Div8 : APB2 clock = HCLK/8
 RCC_HCLK_Div16 : APB2 clock = HCLK/16
Return values
 None.
Notes
 None.