ST STM32F31xx

UM1581
Reset and clock control (RCC)
DocID023800 Rev 1
341/584
 #define: RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
 #define: RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
 #define: RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
 #define: RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
 #define: RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
RCC_APB1_APB2_clock_source
 #define: RCC_HCLK_Div1 ((uint32_t)0x00000000)
 #define: RCC_HCLK_Div2 ((uint32_t)0x00000400)
 #define: RCC_HCLK_Div4 ((uint32_t)0x00000500)
 #define: RCC_HCLK_Div8 ((uint32_t)0x00000600)
 #define: RCC_HCLK_Div16 ((uint32_t)0x00000700)
RCC_APB1_Peripherals
 #define: RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)