ST STM32F31xx

Reset and clock control (RCC)
UM1581
340/584
DocID023800 Rev 1
 #define: RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
 #define: RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
 #define: RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
RCC_AHB_Peripherals
 #define: RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
 #define: RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
 #define: RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
 #define: RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
 #define: RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
 #define: RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
 #define: RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
 #define: RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
 #define: RCC_AHBPeriph_TS RCC_AHBENR_TSEN