Reset and clock control (RCC)
ï‚· #define: RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
ï‚· #define: RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
ï‚· #define: RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
RCC_AHB_Peripherals
ï‚· #define: RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
ï‚· #define: RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
ï‚· #define: RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
ï‚· #define: RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
ï‚· #define: RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
ï‚· #define: RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
ï‚· #define: RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
ï‚· #define: RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
ï‚· #define: RCC_AHBPeriph_TS RCC_AHBENR_TSEN