ST STM32F31xx

UM1581
Reset and clock control (RCC)
DocID023800 Rev 1
349/584
 #define: RCC_PLLMul_13 RCC_CFGR_PLLMULL13
 #define: RCC_PLLMul_14 RCC_CFGR_PLLMULL14
 #define: RCC_PLLMul_15 RCC_CFGR_PLLMULL15
 #define: RCC_PLLMul_16 RCC_CFGR_PLLMULL16
RCC_PREDIV1_division_factor
 #define: RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
 #define: RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
 #define: RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
 #define: RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
 #define: RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
 #define: RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
 #define: RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
 #define: RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8