Analog-to-digital converter (ADC)
ï‚· __IO uint32_t SMPR1
ï‚· __IO uint32_t SMPR2
ï‚· uint32_t RESERVED1
ï‚· __IO uint32_t TR1
ï‚· __IO uint32_t TR2
ï‚· __IO uint32_t TR3
ï‚· uint32_t RESERVED2
ï‚· __IO uint32_t SQR1
ï‚· __IO uint32_t SQR2
ï‚· __IO uint32_t SQR3
ï‚· __IO uint32_t SQR4
ï‚· __IO uint32_t DR
ï‚· uint32_t RESERVED3
ï‚· uint32_t RESERVED4
ï‚· __IO uint32_t JSQR
ï‚· uint32_t RESERVED5
ï‚· __IO uint32_t OFR1
ï‚· __IO uint32_t OFR2
ï‚· __IO uint32_t OFR3
ï‚· __IO uint32_t OFR4
ï‚· uint32_t RESERVED6
ï‚· __IO uint32_t JDR1
ï‚· __IO uint32_t JDR2
ï‚· __IO uint32_t JDR3
ï‚· __IO uint32_t JDR4
ï‚· uint32_t RESERVED7
ï‚· __IO uint32_t AWD2CR
ï‚· __IO uint32_t AWD3CR
ï‚· uint32_t RESERVED8
ï‚· uint32_t RESERVED9
ï‚· __IO uint32_t DIFSEL
ï‚· __IO uint32_t CALFACT
Field Documentation
ï‚· __IO uint32_t ADC_TypeDef::ISR
ï€ ADC Interrupt and Status Register, Address offset: 0x00
ï‚· __IO uint32_t ADC_TypeDef::IER
ï€ ADC Interrupt Enable Register, Address offset: 0x04
ï‚· __IO uint32_t ADC_TypeDef::CR
ï€ ADC control register, Address offset: 0x08
ï‚· __IO uint32_t ADC_TypeDef::CFGR
ï€ ADC Configuration register, Address offset: 0x0C
ï‚· uint32_t ADC_TypeDef::RESERVED0
ï€ Reserved, 0x010
ï‚· __IO uint32_t ADC_TypeDef::SMPR1
ï€ ADC sample time register 1, Address offset: 0x14
ï‚· __IO uint32_t ADC_TypeDef::SMPR2
ï€ ADC sample time register 2, Address offset: 0x18
ï‚· uint32_t ADC_TypeDef::RESERVED1
ï€ Reserved, 0x01C