ST STM32F31xx

Analog-to-digital converter (ADC)
UM1581
50/584
DocID023800 Rev 1
 __IO uint32_t ADC_TypeDef::TR1
 ADC watchdog threshold register 1, Address offset: 0x20
 __IO uint32_t ADC_TypeDef::TR2
 ADC watchdog threshold register 2, Address offset: 0x24
 __IO uint32_t ADC_TypeDef::TR3
 ADC watchdog threshold register 3, Address offset: 0x28
 uint32_t ADC_TypeDef::RESERVED2
 Reserved, 0x02C
 __IO uint32_t ADC_TypeDef::SQR1
 ADC regular sequence register 1, Address offset: 0x30
 __IO uint32_t ADC_TypeDef::SQR2
 ADC regular sequence register 2, Address offset: 0x34
 __IO uint32_t ADC_TypeDef::SQR3
 ADC regular sequence register 3, Address offset: 0x38
 __IO uint32_t ADC_TypeDef::SQR4
 ADC regular sequence register 4, Address offset: 0x3C
 __IO uint32_t ADC_TypeDef::DR
 ADC regular data register, Address offset: 0x40
 uint32_t ADC_TypeDef::RESERVED3
 Reserved, 0x044
 uint32_t ADC_TypeDef::RESERVED4
 Reserved, 0x048
 __IO uint32_t ADC_TypeDef::JSQR
 ADC injected sequence register, Address offset: 0x4C
 uint32_t ADC_TypeDef::RESERVED5[4]
 Reserved, 0x050 - 0x05C
 __IO uint32_t ADC_TypeDef::OFR1
 ADC offset register 1, Address offset: 0x60
 __IO uint32_t ADC_TypeDef::OFR2
 ADC offset register 2, Address offset: 0x64
 __IO uint32_t ADC_TypeDef::OFR3
 ADC offset register 3, Address offset: 0x68
 __IO uint32_t ADC_TypeDef::OFR4
 ADC offset register 4, Address offset: 0x6C
 uint32_t ADC_TypeDef::RESERVED6[4]
 Reserved, 0x070 - 0x07C
 __IO uint32_t ADC_TypeDef::JDR1
 ADC injected data register 1, Address offset: 0x80
 __IO uint32_t ADC_TypeDef::JDR2
 ADC injected data register 2, Address offset: 0x84
 __IO uint32_t ADC_TypeDef::JDR3
 ADC injected data register 3, Address offset: 0x88
 __IO uint32_t ADC_TypeDef::JDR4
 ADC injected data register 4, Address offset: 0x8C
 uint32_t ADC_TypeDef::RESERVED7[4]
 Reserved, 0x090 - 0x09C
 __IO uint32_t ADC_TypeDef::AWD2CR
 ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0
 __IO uint32_t ADC_TypeDef::AWD3CR
 ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4
 uint32_t ADC_TypeDef::RESERVED8
 Reserved, 0x0A8