Analog-to-digital converter (ADC)
ï‚· __IO uint32_t ADC_TypeDef::TR1
ï€ ADC watchdog threshold register 1, Address offset: 0x20
ï‚· __IO uint32_t ADC_TypeDef::TR2
ï€ ADC watchdog threshold register 2, Address offset: 0x24
ï‚· __IO uint32_t ADC_TypeDef::TR3
ï€ ADC watchdog threshold register 3, Address offset: 0x28
ï‚· uint32_t ADC_TypeDef::RESERVED2
ï€ Reserved, 0x02C
ï‚· __IO uint32_t ADC_TypeDef::SQR1
ï€ ADC regular sequence register 1, Address offset: 0x30
ï‚· __IO uint32_t ADC_TypeDef::SQR2
ï€ ADC regular sequence register 2, Address offset: 0x34
ï‚· __IO uint32_t ADC_TypeDef::SQR3
ï€ ADC regular sequence register 3, Address offset: 0x38
ï‚· __IO uint32_t ADC_TypeDef::SQR4
ï€ ADC regular sequence register 4, Address offset: 0x3C
ï‚· __IO uint32_t ADC_TypeDef::DR
ï€ ADC regular data register, Address offset: 0x40
ï‚· uint32_t ADC_TypeDef::RESERVED3
ï€ Reserved, 0x044
ï‚· uint32_t ADC_TypeDef::RESERVED4
ï€ Reserved, 0x048
ï‚· __IO uint32_t ADC_TypeDef::JSQR
ï€ ADC injected sequence register, Address offset: 0x4C
ï‚· uint32_t ADC_TypeDef::RESERVED5[4]
ï€ Reserved, 0x050 - 0x05C
ï‚· __IO uint32_t ADC_TypeDef::OFR1
ï€ ADC offset register 1, Address offset: 0x60
ï‚· __IO uint32_t ADC_TypeDef::OFR2
ï€ ADC offset register 2, Address offset: 0x64
ï‚· __IO uint32_t ADC_TypeDef::OFR3
ï€ ADC offset register 3, Address offset: 0x68
ï‚· __IO uint32_t ADC_TypeDef::OFR4
ï€ ADC offset register 4, Address offset: 0x6C
ï‚· uint32_t ADC_TypeDef::RESERVED6[4]
ï€ Reserved, 0x070 - 0x07C
ï‚· __IO uint32_t ADC_TypeDef::JDR1
ï€ ADC injected data register 1, Address offset: 0x80
ï‚· __IO uint32_t ADC_TypeDef::JDR2
ï€ ADC injected data register 2, Address offset: 0x84
ï‚· __IO uint32_t ADC_TypeDef::JDR3
ï€ ADC injected data register 3, Address offset: 0x88
ï‚· __IO uint32_t ADC_TypeDef::JDR4
ï€ ADC injected data register 4, Address offset: 0x8C
ï‚· uint32_t ADC_TypeDef::RESERVED7[4]
ï€ Reserved, 0x090 - 0x09C
ï‚· __IO uint32_t ADC_TypeDef::AWD2CR
ï€ ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0
ï‚· __IO uint32_t ADC_TypeDef::AWD3CR
ï€ ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4
ï‚· uint32_t ADC_TypeDef::RESERVED8
ï€ Reserved, 0x0A8