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DocID018909 Rev 11 1205/1731

RM0090 Ethernet (ETH): media access control (MAC) with DMA controller

1232

Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)

Address offset: 0x0110

Reset value: 0x0000 0000

The Ethernet MMC transmit interrupt mask register maintains the masks for interrupts

generated when the transmit statistic counters reach half their maximum value. (MSB of the

counter is set). It is a 32-bit wide register.

Ethernet MMC transmitted good frames after a single collision counter

Address offset: 0x014C

Reset value: 0x0000 0000

This register contains the number of successfully transmitted frames after a single collision

in Half-duplex mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TGFM

Reserved

TGFMSCM

TGFSCM

Reserved

rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 TGFM: Transmitted good frames mask

Setting this bit masks the interrupt when the transmitted, good frames, counter reaches half

the maximum value.

Bits 20:16 Reserved, must be kept at reset value.

Bit 15 TGFMSCM: Transmitted good frames more single collision mask

Setting this bit masks the interrupt when the transmitted good frames after more than a

single collision counter reaches half the maximum value.

Bit 14 TGFSCM: Transmitted good frames single collision mask

Setting this bit masks the interrupt when the transmitted good frames after a single collision

counter reaches half the maximum value.

Bits 13:0 Reserved, must be kept at reset value.

313029282726252423222120191817161514131211109876543210

TGFSCC

rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr

Bits 31:0 TGFSCC: Transmitted good frames single collision counter

Transmitted good frames after a single collision counter.

STMicroelectronics STM32F429 Reference Manual

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