EasyManuals Logo

STMicroelectronics STM32F429 Reference Manual

STMicroelectronics STM32F429
1731 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #63 background imageLoading...
Page #63 background image
DocID018909 Rev 11 63/1731
RM0090 Memory and bus architecture
112
2.1.4 DMA memory bus
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal SRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the
FSMC/FMC.
2.1.5 DMA peripheral bus
This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is
used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.
The targets of this bus are the AHB and APB peripherals plus data memories: internal
SRAMs (SRAM1, SRAM2 and SRAM3) and external memories through the FSMC/FMC.
2.1.6 Ethernet DMA bus
This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by
the Ethernet DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory, and
external memories through the FSMC/FMC.
2.1.7 USB OTG HS DMA bus
This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is
used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAMs (SRAM1, SRAM2, SRAM3), internal Flash memory, and
external memories through the FSMC/FMC.
2.1.8 LCD-TFT controller DMA bus
This bus connects the LCD controller DMA master interface to the BusMatrix. It is used by
the LCD-TFT DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAMs (SRAM1, SRAM2, SRAM3), external memories through FMC,
and internal Flash memory.
2.1.9 DMA2D bus
This bus connect the DMA2D master interface to the BusMatrix. This bus is used by the
DMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data
memories: internal SRAMs (SRAM1, SRAM2, SRAM3), external memories through FMC,
and internal Flash memory.
2.1.10 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
round-robin algorithm.

Table of Contents

Other manuals for STMicroelectronics STM32F429

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the STMicroelectronics STM32F429 and is the answer not in the manual?

STMicroelectronics STM32F429 Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F429
CategoryController
LanguageEnglish

Related product manuals