To Next Page

To Previous Page

Analog-to-digital converter (ADC) RM0090

404/1731 DocID018909 Rev 11

13.8.3 Conversions without DMA and without overrun detection

It may be useful to let the ADC convert one or more channels without reading the data each

time (if there is an analog watchdog for instance). For that, the DMA must be disabled

(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this

configuration, overrun detection is disabled.

13.9 Multi ADC mode

In devices with two ADCs or more, the Dual (with two ADCs) and Triple (with three ADCs)

ADC modes can be used (see Figure 51).

In multi ADC mode, the start of conversion is triggered alternately or simultaneously by the

ADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the

MULTI[4:0] bits in the ADC_CCR register.

Note: In multi ADC mode, when configuring conversion trigger by an external event, the

application must set trigger by the master only and disable trigger by slaves to prevent

spurious triggers that would start unwanted slave conversions.

The four possible modes below are implemented:

• Injected simultaneous mode

• Regular simultaneous mode

• Interleaved mode

• Alternate trigger mode

It is also possible to use the previous modes combined in the following ways:

• Injected simultaneous mode + Regular simultaneous mode

• Regular simultaneous mode + Alternate trigger mode

Note: In multi ADC mode, the converted data can be read on the multi-mode data register

(ADC_CDR). The status bits can be read in the multi-mode status register (ADC_CSR).

STMicroelectronics STM32F429 Reference Manual

Other manuals for STMicroelectronics STM32F429