DocID018909 Rev 11 215/1731
RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
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A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the RCC Backup domain control
register (RCC_BDCR).
2. V
DD
or V
BAT
power on, if both supplies have previously been powered off.
7.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
• HSI oscillator clock
• HSE oscillator clock
• Main PLL (PLL) clock
The devices have the two following secondary clock sources:
• 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and,
optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.
• 32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
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