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LCD-TFT Controller (LTDC) RM0090

500/1731 DocID018909 Rev 11

16.7.14 LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2)

Address offset: 0x84 + 0x80 x (Layerx -1), Layerx = 1 or 2

Reset value: 0x0000 0000

16.7.15 LTDC Layerx Window Horizontal Position Configuration Register

(LTDC_LxWHPCR) (where x=1..2)

This register defines the Horizontal Position (first and last pixel) of the layer 1 or 2 window.

The first visible pixel of a line is the programmed value of AHBP[10:0] bits + 1 in the

LTDC_BPCR register.

The last visible pixel of a line is the programmed value of AAW[10:0] bits in the

LTDC_AWCR register. All values within this range are allowed.

Address offset: 0x88 + 0x80 x (Layerx -1), Layerx = 1 or 2

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

CLUTEN

Reserved

COLKEN LEN

rw rw rw

Bits 31:5 Reserved, must be kept at reset value

Bit 4 CLUTEN: Color Look-Up Table Enable

This bit is set and cleared by software.

0: Color Look-Up Table disable

1: Color Look-Up Table enable

The CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color Look-Up

Table (CLUT) on page 487

Bit 3 Reserved, must be kept at reset value

Bit 2 Reserved, must be kept at reset value

Bit 1 COLKEN: Color Keying Enable

This bit is set and cleared by software.

0: Color Keying disable

1: Color Keying enable

Bit 0 LEN: Layer Enable

This bit is set and cleared by software.

0: Layer disable

1: Layer enable

STMicroelectronics STM32F429 Reference Manual

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