DocID018909 Rev 11 369/1731
RM0090 Chrom-Art Accelerator™ controller (DMA2D)
372
11.5.17 DMA2D output offset register (DMA2D_OOR)
Address offset: 0x0040
Reset value: 0x0000 0000
11.5.18 DMA2D number of line register (DMA2D_NLR)
Address offset: 0x0044
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LO[13:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value
Bits 13:0 LO[13: 0]: Line Offset
Line offset used for the output (expressed in pixels). This value is used for the address
generation. It is added at the end of each line to determine the starting address of the
next line. These bits can only be written when data transfers are disabled. Once the
transfer has started, they are read-only.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PL[13:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NL[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value
Bits 29:16 PL[13: 0]: Pixel per lines
Number of pixels per lines of the area to be transferred. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
If any of the input image format is 4-bit per pixel, pixel per lines must be even.
Bits 15:0 NL[15: 0]: Number of lines
Number of lines of the area to be transferred. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
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