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LCD-TFT Controller (LTDC) RM0090

496/1731 DocID018909 Rev 11

16.7.8 LTDC Interrupt Enable Register (LTDC_IER)

This register determines which status flags generate an interrupt request by setting the

corresponding bit to 1.

Address offset: 0x34

Reset value: 0x0000 0000

Bits 31:24 Reserved, must be kept at reset value

Bits 23:16 BCRED[7:0]: Background Color Red value

These bits configure the background red value

Bits 15:8 BCGREEN[7:0]: Background Color Green value

These bits configure the background green value

Bits 7:0 BCBLUE[7:0]: Background Color Blue value

These bits configure the background blue value

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

RRIE TERRIE FUIE LIE

rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value

Bit 3 RRIE: Register Reload interrupt enable

This bit is set and cleared by software

0: Register Reload interrupt disable

1: Register Reload interrupt enable

Bit 2 TERRIE: Transfer Error Interrupt Enable

This bit is set and cleared by software

0: Transfer Error interrupt disable

1: Transfer Error interrupt enable

Bit 1 FUIE: FIFO Underrun Interrupt Enable

This bit is set and cleared by software

0: FIFO Underrun interrupt disable

1: FIFO Underrun Interrupt enable

Bit 0 LIE: Line Interrupt Enable

This bit is set and cleared by software

0: Line interrupt disable

1: Line Interrupt enable

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