STMicroelectronics STM32F429 Reference Manual

DMA controller (DMA) RM0090
320/1731 DocID018909 Rev 11
Table 48: FIFO threshold configurations.
In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data
size can be: 1 (byte), 2 (half-word) or 4 (word)).
Incomplete Burst transfer at the end of a DMA transfer may happen if one of the following
conditions occurs:
• For the AHB peripheral port configuration: the total number of data items (set in the
DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size
• For the AHB memory port configuration: the number of remaining data items in the
FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the
data size
In such cases, the remaining data to be transferred will be managed in single mode by the
DMA, even if a burst transaction was requested during the DMA stream configuration.
Note: When burst transfers are requested on the peripheral AHB port and the FIFO is used
(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to
avoid permanent underrun or overrun conditions, depending on the DMA stream direction:
If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with
PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.
This rule ensures that enough FIFO space at a time will be free to serve the request from
the peripheral.
Table 48. FIFO threshold configurations
MSIZE FIFO level MBURST = INCR4 MBURST = INCR8 MBURST = INCR16
Byte
1/4 1 burst of 4 beats
forbidden
forbidden1/2 2 bursts of 4 beats 1 burst of 8 beats
3/4 3 bursts of 4 beats
forbidden
Full 4 bursts of 4 beats 2 bursts of 8 beats 1 burst of 16 beats
Half-word
1/4
forbidden
forbidden
forbidden
1/2 1 burst of 4 beats
3/4
forbidden
Full 2 bursts of 4 beats 1 burst of 8 beats
Word
1/4
forbidden
forbidden
1/2
3/4
Full 1 burst of 4 beats

STMicroelectronics STM32F429 Specifications

General

Brand	STMicroelectronics
Model	STM32F429
Category	Controller
Language	English