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STMicroelectronics STM32F429 Reference Manual

STMicroelectronics STM32F429
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Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1218/1731 DocID018909 Rev 11
Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR)
Address offset: 0x1010
Reset value: 0x0000 0000
The Transmit descriptor list address register points to the start of the transmit descriptor list.
The descriptor lists reside in the STM32F4xx's physical memory space and must be word-
aligned. The DMA internally converts it to bus-width-aligned address by taking the
corresponding LSB to low. Writing to the ETH_DMATDLAR register is permitted only when
transmission has stopped. Once transmission has stopped, the ETH_DMATDLAR register
can be written before the transmission Start command is given.
Ethernet DMA status register (ETH_DMASR)
Address offset: 0x1014
Reset value: 0x0000 0000
The Status register contains all the status bits that the DMA reports to the application. The
ETH_DMASR register is usually read by the software driver during an interrupt service
routine or polling. Most of the fields in this register cause the host to be interrupted. The
ETH_DMASR register bits are not cleared when read. Writing 1 to (unreserved) bits in
ETH_DMASR register[16:0] clears them and writing 0 has no effect. Each field (bits [16:0])
can be masked by masking the appropriate bit in the ETH_DMAIER register.
Bits 31:0 SRL: Start of receive list
This field contains the base address of the first descriptor in the receive descriptor list. The
LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by
the DMA. Hence these LSB bits are read only.
313029282726252423222120191817161514131211109876543210
STL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 STL: Start of transmit list
This field contains the base address of the first descriptor in the transmit descriptor list. The
LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero
by the DMA. Hence these LSB bits are read-only.
313029282726252423222120191817161514131211109876543210
Reserved
TSTS
PMTS
MMCS
Reserved
EBS
TPS
RPS
NIS
AIS
ERS
FBES
Reserved
ETS
RWTS
RPSS
RBUS
RS
TUS
ROS
TJTS
TBUS
TPSS
TS
rrr rrrrrrrrr
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w1
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rc-
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rc-
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rc-
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rc-
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rc-
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rc-
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STMicroelectronics STM32F429 Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32F429
CategoryController
LanguageEnglish

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