STMicroelectronics STM32F429 Reference Manual

DocID018909 Rev 11 1509/1731
RM0090 USB on-the-go high-speed (OTG_HS)
1529
1. Before disabling any OUT endpoint, the application must enable Global OUT NAK
mode in the core.
– SGONAK = 1 in OTG_HS_DCTL
2. Wait for the GONAKEFF interrupt (OTG_HS_GINTSTS)
3. Disable the required OUT endpoint by programming the following fields:
– EPDIS = 1 in OTG_HS_DOEPCTLx
– SNAK = 1 in OTG_HS_DOEPCTLx
4. Wait for the EPDISD interrupt (OTG_HS_DOEPINTx), which indicates that the OUT
endpoint is completely disabled. When the EPDISD interrupt is asserted, the core also
clears the following bits:
– EPDIS = 0 in OTG_HS_DOEPCTLx
– EPENA = 0 in OTG_HS_DOEPCTLx
5. The application must clear the Global OUT NAK bit to start receiving data from other
nondisabled OUT endpoints.
– SGONAK = 0 in OTG_HS_DCTL
• Generic nonisochronous OUT data transfers
This section describes a regular nonisochronous OUT data transfer (control, bulk, or
interrupt).
Application requirements:
1. Before setting up an OUT transfer, the application must allocate a buffer in the memory
to accommodate all data to be received as part of the OUT transfer.
2. For OUT transfers, the transfer size field in the endpoint’s transfer size register must be
a multiple of the maximum packet size of the endpoint, adjusted to the DWORD
boundary.
– transfer size[EPNUM] = n × (MPSIZ[EPNUM] + 4 – (MPSIZ[EPNUM] mod 4))
– packet count[EPNUM] = n
– n > 0
3. On any OUT endpoint interrupt, the application must read the endpoint’s transfer size
register to calculate the size of the payload in the memory. The received payload size
can be less than the programmed transfer size.
– Payload size in memory = application programmed initial transfer size – core
updated final transfer size
– Number of USB packets in which this payload was received = application
programmed initial packet count – core updated final packet count
Internal data flow:
1. The application must set the transfer size and packet count fields in the endpoint-
specific registers, clear the NAK bit, and enable the endpoint to receive the data.
2. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive
FIFO, as long as there is space in the receive FIFO. For every data packet received on
the USB, the data packet and its status are written to the receive FIFO. Every packet

STMicroelectronics STM32F429 Specifications

General

Brand	STMicroelectronics
Model	STM32F429
Category	Controller
Language	English