Flexible static memory controller (FSMC) RM0090
1568/1731 DocID018909 Rev 11
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of a write-to-read (and read-to
write) transaction. The programmed bus turnaround delay is inserted between an
asynchronous read (muxed or D mode) or a write transaction and any other
asynchronous/synchronous read or write to/from a static bank (for a read operation, the bank
can be the same or a different one; for a write operation, the bank can be different except in r
muxed or D mode).
In some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN
values:
– No bus turnaround delay is inserted between two consecutive asynchronous write transfers
to the same static memory bank except in muxed and D mode.
– A bus turnaround delay of 1 FSMC clock cycle is inserted between:
– Two consecutive synchronous write operations (in burst or single mode) to different
static banks.
– A synchronous write access (in burst or single mode) and a synchronous read from
the same or a different bank.
– An asynchronous and a synchronous write to any static or dynamic memory bank
except in muxed and D modes.
– An asynchronous (modes 1, 2, A, B or C) read and a read operation from another
static bank.
– A bus turnaround delay of 2 FSMC clock cycles is inserted between:
– Two consecutive synchronous write accesses (in burst or single mode) to the same
bank
– A synchronous write access (in burst or single mode) and an asynchronous write or
read transfer to/from a static memory bank.
– Two consecutive synchronous read accesses (in burst or single mode) followed by a
any synchronous/asynchronous read or write from/to another static memory bank.
– A bus turnaround delay of 3 FSMC clock cycles is inserted between:
– Two consecutive synchronous write operations (in burst or single mode) to different
static banks.
– A synchronous write access (in burst or single mode) and a synchronous read
access from the same or to a different bank.
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
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