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DocID018909 Rev 11 355/1731

RM0090 Chrom-Art Accelerator™ controller (DMA2D)

372

Bit 10 TWIE: Transfer watermark interrupt enable

This bit is set and cleared by software.

0: TW interrupt disable

1: TW interrupt enable

Bit 9 TCIE: Transfer complete interrupt enable

This bit is set and cleared by software.

0: TC interrupt disable

1: TC interrupt enable

Bit 8 TEIE: Transfer error interrupt enable

This bit is set and cleared by software.

0: TE interrupt disable

1: TE interrupt enable

Bits 7:3 Reserved, must be kept at reset value

Bit 2 ABORT: Abort

This bit can be used to abort the current transfer. This bit is set by software and is

automatically reset by hardware when the START bit is reset.

0: No transfer abort requested

1: Transfer abort requested

Bit 1 SUSP: Suspend

This bit can be used to suspend the current transfer. This bit is set and reset by

software. It is automatically reset by hardware when the START bit is reset.

0: Transfer not suspended

1: Transfer suspended

Bit 0 START: Start

This bit can be used to launch the DMA2D according to the parameters loaded in the

various configuration registers. This bit is automatically reset by the following events:

– At the end of the transfer

– When the data transfer is aborted by the user application by setting the ABORT

bit in DMA2D_CR

– When a data transfer error occurs

– When the data transfer has not started due to a configuration error or another

transfer operation already ongoing (automatic CLUT loading).

STMicroelectronics STM32F429 Reference Manual

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