Appendix B Functional Description 199
The following sections provide brief descriptions of DSIMMs, VSIMMs, and
NVSIMMs, and identifies the maximum available memory capacities based on
possible memory allocations.
DSIMM
The SPARCstation 20 memory system has a 144-bit-wide data path. The
144-bit-wide path is divided into a 128-bit-wide data path and 16 bits of error
correcting code (ECC). Through the Scalable Memory Controller (SMC), the
60-nanosecond DSIMMs receive control, address information, and data. The
maximum available DSIMM memory capacities, based upon possible memory
allocations, are as follows:
â– Eight DSIMMs, zero VSIMMs, zero DVSIMMS: 8 x 64 Mbytes or 512 Mbytes
â– Seven DSIMMS with one VSIMM or one DVSIMM: 7 x 64 Mbytes or 448 Mbytes
â– Six DSIMMS with two VSIMMs or one VSIMM and one DVSIMM: 6 x 64 Mbytes
or 384 Mbytes
TABLE B-2 lists the DSIMM DRAM densities supported by the SMC. FIGURE B-2
illustrates the DSIMM memory system.
TABLE B-1 Memory Allocations
Memory
Allocation
DSIMM VSIMM NVSIMM
8 (max.) 0 0
710
7 0 1 (max.)
6 2 (max.) 0
611
TABLE B-2 DSIMM DRAM Densities
RAM Density Number of RAMs Capacity Type
4-Mbit 1M x 4 36 16 Mbytes ECC DRAM
8-Mbit 2M x 4 36 32 Mbytes ECC DRAM
16-Mbit 4M x 4 36 64 Mbytes ECC DRAM
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