Circuit Descriptions
5–20
1502C MTDR Service Manual
All digital clocks from the instrument are derived from a 20 MHz crystal oscillator,
U2031. Flip-flops U2042A and U2042B divide the clock frequency to 10 MHz and
5 MHz respectively. The 5 MHz output is provided to the microprocessor and to
TP2041.
Gate U2034B decodes one of the four states if U2042 and provides a 5 MHz pulse
to U2033B. Flip-flop U2033B is clocked by the 20 MHz clock and divides the 5
MHz signals to 2.5 MHz synchronously with the 20 MHz. The 2.5 MHz clock is
further divided to 1.25 MHz by U2025A and 625 kHz by U2025B.
The PRT, coarse delay, and real-time counters are contained in a triple, 16-bit,
programmable counter device, U2030. The PRT and coarse delay counters are
clocked at the 2.5 MHz rate. The output of the PRT counter, pin 10 of U2030, is
applied to the trigger input of the coarse delay counter as a start-count signal. The
negative-going pulse from the coarse delay counter, pin 13 of U2030, is input to a
two-stage shift register, U2032C and U2032D. This shift register is also clocked at
2.5 MHz and serves to delay the signal and reduce its skew relative to the 20 MHz
clock. The Q
(inverted output) of U2032C is a positive-going pulse that is supplied
to a three-stage shift register, U2036B, U2036D, and U2036A, which is clocked at
20 MHz from inverter U2034A. The leading edge of the pulse is decoded by NAND
gate U2045B, which also ANDs the signal with the 20 MHz clock from inverter
U2045A. The resulting driver trigger pulse is a negative-going pulse of nominally
25 ns width. The falling edge of this pulse is determined by the edge of the 20 MHz
input to gate U2045B and is used as the driver trigger.
The coarse delay pulse from shift register U2032D and U2032C us decoded by NOR
gate U2034C to detect the pulse rising edge (end of the negative pulse). The
resulting positive pulse is 400 ns wide (one cycle of the 2.5 MHz clock). This pulse
is shifted through flip-flop U2036C to synchronize it with the 20 MHz clock and
applied to the count enable input of U2037, a four-bit programmable counter.
Counter U2037 will have been preset to a count of 8 through 15 by the processor
through latch U2043 with CS11
. While the count enable pulse is present, it will
count exactly eight times at the 20 MHz rate, thus passing through count 15 after
0 through 7 clock pulses. The terminal count (TC) output of U2037 is a decode of
count 15. Thus this signal creates the fine delay pulse after the programmed delay.
This positive-going pulse is gated with the 20 MHz clock by NAND gate U2045C
to provide a 25 ns negative-going pulse for the ramp trigger. Ramp timing is derived
from the trigger falling edge.
The end of the coarse delay, detected by gate U2034C, is used to clock U2027A,
which generates an interrupt request to inform the processor that a sample is being
taken. An acknowledge pulse, CS16
, from the address decoder resets this flip-flop.
The logic level driver trigger from the digital timebase is first amplified by transistor
stage Q9021. The trigger is capacitively coupled through C8022 and R9027 to shift
it to analog levels. The collector of Q9021 is clamped to –0.5 VDC between pulses
by CR8020 and rises to +6 VDC peak during the 25 ns pulse. This signal is applied
Digital Timebase
Analog Timebase
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...
Need help?
General
